This invention relates in general to electrically erasable and programmable read-only-memory (EEPROM) devices and in particular, to the construction and operation of high density EEPROM devices and their erase circuitry.
High density EEPROM devices generally include a large array of EEPROM cells and circuitry for programming, erasing, and reading the array of EEPROM cells. A number of design objectives are considered when laying-out such a device in an integrated circuit (IC). General IC design objectives include minimizing the IC's die size to minimize its cost, and forming a square-shaped IC die to enhance the IC's manufacturability and as a consequence, to minimize its cost.
Application specific design objectives are also considered. For example, U.S. Pat. No. 5,297,148, which is incorporated herein by this reference, describes a flash EEPROM system which emulates a magnetic disk drive. Included in the flash EEPROM system are one or more EEPROM chips partitioned into sectors where all memory cells within a sector are erased together. Associated with each sector is an erase latch. Sectors to be erased are then "tagged" for erasure by an address decoder setting their corresponding erase latches.
There are a number of different ways in which the flash EEPROM cells of such an EEPROM chip can be physically organized. For example, the EEPROM cells may be organized into a sector-wide array, wherein each row of memory cells consisting of a sector of data may be erased together by connecting their erase gates to a common erase line and applying appropriate voltages to the EEPROM cells. An example of such an array is depicted in FIG. 1.
Another way of partitioning such an EEPROM chip is to organize its memory cells into an array which is a fraction of a sector wide. For example, if the array is half-a-sector wide, then by connecting the erase gates of the memory cells in a pair of rows together, the pair of rows of memory cells comprising a sector of data may be erased together.
Still another way of partitioning such an EEPROM chip is to organize its memory cells into an array which is two sectors wide. If the array is two sectors wide, then a first half of the memory cells comprising a first sector of data in each row may be connected together and accessed on one side of the array, and a second half of the memory cells comprising a second sector of data in each row may be connected together and accessed on an opposite side of the array.
It is generally impractical, however, to organize the memory cells into an array which is more than two sectors wide. For example, if the EEPROM chip is organized into a three sector wide array, then the first and third sectors of data respectively formed from the first and last thirds of the memory cells in each row by having their erase gates connected together, can be respectively accessed on opposite sides of the array, but access to the second sector of data formed from the middle (or second) third of the memory in each row by having its erase gates connected together, is difficult.
Accordingly, to facilitate concurrent erasure of tagged sectors of data in an EEPROM chip, the number of columns in the EEPROM chip's array of EEPROM cells may be practically limited to two sectors, a sector, or a fraction of a sector of data. As the size of such EEPROM cell arrays increase, however, with each new generation of high density flash EEPROM devices, it becomes increasingly more difficult to design such new generations so as to generally satisfy such columnar array structure requirement and the aforementioned general design considerations. In particular, by constraining the expansion of memory cells in only one direction (e.g., increasing the number of rows in such arrays, but not the number of columns), it becomes increasingly more difficult to lay-out such high density EEPROM chips in a square-shaped die.